FastPix is a reconfigurable low light-level (LLL) hybrid sensor that can be scaled to arbitrarily large areas and that aims to detect the time of arrival of single photons with a time resolution (SPTR) close to 10 ps. The FastPix performance will be at least one order of magnitude better than any existing technology in time, spatial resolution, rate, and power consumption. FastPix brings a revolution in medical imaging by enabling reconstruction-less PET, a new era in LIDAR by achieving millimetric spatial resolution requiring no averaging, and a strong impact in other fields such as fluorescence imaging.

Neither large channel area (>> 1 mm2/ch) analog nor digital SiPMs achieve a SPTR below 100 ps. The detector input capacitance limits the time resolution in analog SiPMS and the power consumption and data readout in digital SiPMs. In FastPix, small groups of microcells will be connected in parallel to ultrafast readout electronics using 3D integration techniques. The readout electronics will implement an innovative signal processing and active analog summation to allow to produce large area sensors with a configurable granularity. The time resolution of FastPix shall approach to the limiting intrinsic time resolution of a single microcell (SPAD).

The readout electronics should be designed using very deep submicron (UDSM) technologies (down to 28 nm) to develop ultra-fast (<< 10ps resolution) low power consumption (<1mW) Time to Digital Converters (TDCs) banks and clock distribution networks. However, these UDSM processes pose challenges, particularly to the analog frontend design.

Moreover, the readout circuit will be highly reconfigurable to make it compatible with other promising sensors as pixelated Micro Channel Plates (MCPs), Tynodes and others. In all the cases the same concept can be applied: building large area detectors with 10 ps resolution by electronic smart combination of small groups of pixels. This also allows programming the system for different granularities and to optimise the total system power consumption and output data bandwidth.

The final goal of FastPix will be to develop hybrid prototypes that can be tiled seamlessly on four sides to produce large detection areas (>> 1 cm2). However, this implies developing custom sensors, electronics and 3D interconnects and hence it requires the completion of a second phase of ATTRACT.

In this proposal, the emphasis is on the development of novel Pixelated Integrated Circuit (IC) architectures for reconfigurable fast front-end and TDC banks in Ultra Deep Sub-Micron technologies as 28 nm CMOS, and hence the name FastICpix.

The final deliverable of phase I is a Monte Carlo simulation, including the IC described at transistor level and the sensor model plus interconnects, which shall validate the FastPix concept, 10 ps time resolution for large area sensors, and it will justify its implementation in the second phase of ATTRACT.